Design Rule Verification Report
Date:
30/01/2025
Time:
19:18:58
Elapsed Time:
00:00:00
Filename:
C:\Users\asad1\OneDrive\Documents\APPs_DATA\GitHub\Table-de-Mixage\02-Detection_et_Ampli\Detection_et_Amplification.PcbDoc
Warnings:
0
Rule Violations:
32
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=0.254mm) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
3
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Width Constraint (Min=1mm) (Max=2mm) (Preferred=1mm) (All)
0
Routing Layers(All)
0
Routing Via (MinHoleWidth=0.254mm) (MaxHoleWidth=0.254mm) (PreferredHoleWidth=0.254mm) (MinWidth=0.508mm) (MaxWidth=0.508mm) (PreferedWidth=0.508mm) (All)
7
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) and Width Constraints (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (All)
0
SMD Neck-Down Constraint (Percent=100%) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
0
Minimum Annular Ring (Minimum=0.254mm) (All)
0
Hole Size Constraint (Min=0.254mm) (Max=7.62mm) (All)
0
Pads and Vias to follow the Drill pairs settings
0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)
0
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
12
Silk to Silk (Clearance=0.254mm) (All),(All)
0
Net Antennae (Tolerance=0mm) (All)
0
Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli'))
10
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (All),(All)
0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
0
Total
32
Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net GND Between Pad J1-5(1.5mm,21.27mm) on Multi-Layer And Pad J1-3(1.5mm,26.35mm) on Multi-Layer
Un-Routed Net Constraint: Net GND Between Pad J1-7(1.5mm,16.19mm) on Multi-Layer And Pad J1-5(1.5mm,21.27mm) on Multi-Layer
Un-Routed Net Constraint: Net NetR5_0 Between Pad R5-0(18.502mm,31.979mm) on Multi-Layer And Pad R7-1(20.041mm,31.521mm) on Multi-Layer
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Routing Via (MinHoleWidth=0.254mm) (MaxHoleWidth=0.254mm) (PreferredHoleWidth=0.254mm) (MinWidth=0.508mm) (MaxWidth=0.508mm) (PreferedWidth=0.508mm) (All)
Routing Via Style: Via (4.267mm,11.1mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (4.267mm,16.058mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (4.293mm,6.215mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (4.521mm,28.769mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (4.582mm,18.529mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (6.383mm,20.331mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
Routing Via Style: Via (6.909mm,31.364mm) from Top Layer to Bottom Layer Actual Size : 1.27mm Actual Hole Size : 0.711mm
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Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-0(15.354mm,9.624mm) on Multi-Layer And Track (14.504mm,8.574mm)(14.504mm,10.574mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R1-1(7.354mm,9.624mm) on Multi-Layer And Track (8.204mm,8.574mm)(8.204mm,10.574mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R3-0(28.891mm,9.709mm) on Multi-Layer And Track (28.041mm,8.659mm)(28.041mm,10.659mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R3-1(20.891mm,9.709mm) on Multi-Layer And Track (21.741mm,8.659mm)(21.741mm,10.659mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R4-0(7.354mm,12.902mm) on Multi-Layer And Track (8.204mm,11.952mm)(8.204mm,13.952mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R4-1(15.354mm,12.902mm) on Multi-Layer And Track (14.504mm,11.952mm)(14.504mm,13.952mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R5-0(18.502mm,31.979mm) on Multi-Layer And Track (17.652mm,30.929mm)(17.652mm,32.929mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R5-1(10.502mm,31.979mm) on Multi-Layer And Track (11.352mm,30.929mm)(11.352mm,32.929mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R7-0(28.041mm,31.521mm) on Multi-Layer And Track (27.191mm,30.471mm)(27.191mm,32.471mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R7-1(20.041mm,31.521mm) on Multi-Layer And Track (20.891mm,30.471mm)(20.891mm,32.471mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R8-0(8.279mm,26.619mm) on Multi-Layer And Track (9.129mm,25.669mm)(9.129mm,27.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
Silk To Solder Mask Clearance Constraint: (0.123mm < 0.254mm) Between Pad R8-1(16.279mm,26.619mm) on Multi-Layer And Track (15.429mm,25.669mm)(15.429mm,27.669mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.123mm]
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Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli'))
Room Definition: Between DIP Component U1-TL084CN (18mm,20mm) on Top Layer And Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli'))
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And SIP Component J1-90121-0770 (-1.5mm,20mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component J_Pot1-691102710002 (36mm,10mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component J_Pot2-691102710002 (36mm,30mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R1-Res_3.5x6.5mm_TH (15.354mm,9.624mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R3-Res_3.5x6.5mm_TH (28.891mm,9.709mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R4-Res_3.5x6.5mm_TH (7.354mm,12.902mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R5-Res_3.5x6.5mm_TH (18.502mm,31.979mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R7-Res_3.5x6.5mm_TH (28.041mm,31.521mm) on Top Layer
Room Definition: Between Room Detection_et_Ampli (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('Detection_et_Ampli')) And Small Component R8-Res_3.5x6.5mm_TH (8.279mm,26.619mm) on Top Layer
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